Semiconductor device

ABSTRACT

The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.13/937,846, filed Jul. 9, 2013, which claims benefit of priority fromthe prior Japanese Application No. 2012-156891, filed on Jul. 12, 2012;the entire contents of all of which are incorporated herein byreference.

BACKGROUND

The present invention relates to a semiconductor device, and, forexample, to a technique that is effectively applied to a semiconductordevice including a power device made of a nitride semiconductormaterial.

Japanese Unexamined Patent Application Publication No. Hei7 (1995)-45829discloses a configuration in which a plurality of contact holes isconnected to a metal wiring portion in a drain diffusion region, and theplurality of contact holes is also connected to a metal wiring portionin a source diffusion region.

Also, Japanese Patent No. 3086713 discloses a technique in which aplurality of source contact regions that joins a source electrode to anondivided source region is provided.

SUMMARY

Nowadays, higher-efficient use of energy in preparation for a low carbonsociety represents an important and prompt issue. In order to use thehigh efficiency of energy, for example, because the effect of reducing apower loss in an inverter contributes to the high efficiency of theenergy, it is important to develop the power device configuring theinverter. In the research and development status, as a material of thepower device, a change from Si (silicon) to GaN (gallium nitride) hasbeen considered. This is because there can be provided a power device ofa high performance which can perform both of a reduction in an onresistance and a withstand voltage with the use of GaN (gallium nitride)since GaN (gallium nitride) is larger in breakdown field intensity andband gap than Si (silicon).

However, because the power device deals with a large current, forexample, when an ohmic electrode that comes in ohmic contact with anitride semiconductor layer is used, a current density flowing in theohmic electrode becomes large. For that reason, a risk that anelectromigration occurring in the ohmic electrode leads to thegeneration of voids and disconnection is increased.

The other problems and novel features will become apparent from thedescription of the present specification and the attached drawings.

According to an aspect of the present invention, there is provided afield effect transistor including a first ohmic electrode having aplurality of first unit electrodes that comes in ohmic contact with anitride semiconductor layer, and is separated from each other. Further,the electric field transistor according to the aspect of the presentinvention includes a second ohmic electrode having a plurality of secondunit electrodes that comes in ohmic contact with the nitridesemiconductor layer, and is separated from each other, in which thesecond ohmic electrode is separated from the first ohmic electrode. Theplurality of first unit electrodes and the plurality of second unitelectrodes each include an aluminum film.

According to the aspect of the present invention, the reliability of thefield effect transistor using a nitride semiconductor material can beimproved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view illustrating a configuration example of a powerMOSFET in a related art;

FIG. 2 is a cross-sectional view taken along a line A-A in FIG. 1;

FIG. 3 is a plan view illustrating a configuration example of a powerMOSFET according to a first embodiment;

FIG. 4 is a partially enlarged plan view of a source electrodeillustrated in FIG. 3;

FIG. 5 is a cross-sectional view taken along a line A-A in FIG. 3;

FIG. 6 is a graph illustrating a current to voltage characteristic in anohmic contact;

FIG. 7 is a cross-sectional view of a source electrode mainly takenalong a B-B line of FIG. 3;

FIG. 8 is a cross-sectional view illustrating a process of manufacturinga semiconductor device according to the first embodiment;

FIG. 9 is a cross-sectional view illustrating a process of manufacturingthe semiconductor device subsequent to FIG. 8;

FIG. 10 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 9;

FIG. 11 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 10;

FIG. 12 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 11;

FIG. 13 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 12;

FIG. 14 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 13;

FIG. 15 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 14;

FIG. 16 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 15;

FIG. 17 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 16;

FIG. 18 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device according to the firstembodiment;

FIG. 19 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 18;

FIG. 20 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 19;

FIG. 21 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 20;

FIG. 22 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 21;

FIG. 23 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 22;

FIG. 24 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 23;

FIG. 25 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 24;

FIG. 26 is a graph illustrating a relationship between a current density(A/cm²) and the number of unit electrodes;

FIG. 27 is a diagram illustrating a cross-section of a power MOSFETaccording to a first modification;

FIG. 28 is a diagram illustrating a plan configuration of a power MOSFETaccording to a second modification;

FIG. 29 is a diagram illustrating a plan configuration of a power MOSFETaccording to a third modification;

FIG. 30 is a diagram illustrating a cross-section of a power MOSFETaccording to a second embodiment;

FIG. 31 is a cross-sectional view illustrating a process ofmanufacturing a semiconductor device according to the second embodiment;

FIG. 32 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 31;

FIG. 33 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 32;

FIG. 34 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 33;

FIG. 35 is a cross-sectional view illustrating a process ofmanufacturing the semiconductor device subsequent to FIG. 34;

FIG. 36 is a diagram illustrating a circuit diagram of a three-phasemotor according to a third embodiment; and

FIG. 37 is a diagram illustrating a cross-section of a power MOSFETaccording to a fourth embodiment.

DETAILED DESCRIPTION

The following embodiments are divided into a plurality of sections andembodiments, when necessary for the sake of convenience. Therefore,unless clearly indicated otherwise, the divided sections or embodimentsare not irrelevant to one another, but one section or embodiment has arelation of modifications, details and supplementary explanations tosome or all of the other embodiments.

In addition, in the following embodiments, when the number (includingcount, figure, amount, and range) of the components is mentioned, thenumber of components is not limited to a specific number and may begreater than, less than or equal to the specific number, unless clearlyspecified otherwise and definitely limited to the specific number inprinciple.

Furthermore, there is no need to say that, in the following embodiments,the components (including component steps, etc.) are not alwaysessential, unless clearly specified otherwise and considered to bedefinitely essential in principle.

Similarly, when shapes and positional relationships, etc. of thecomponents are mentioned in the following embodiments, the componentswill have shapes substantially analogous or similar to their shapes orthe like, unless clearly defined otherwise and considered not to bedefinite in principle. This is applied likewise to the above-describednumerical values and ranges as well.

In addition, in all the drawings for explaining the embodiments, thesame components are indicated by the same reference numerals inprinciple, and so a repeated description thereof will be omitted. Also,hatching may be used even in plan views to make it easy to read thedrawings.

First Embodiment Description of Related Art

First, before a semiconductor device according to a first embodimentwill be described, a semiconductor device in a related art will bedescribed. Then, after a room for improvement in the related art isdescribed, a technical concept of the first embodiment will bedescribed.

FIG. 1 is a plan view illustrating a configuration example of a powerMOSFET (Metal Oxide Semiconductor Field Effect Transistor) in a relatedart. As illustrated in FIG. 1, in the power MOSFET of the related art,gate pads GP are each arranged on a left end and a right end of a paperplane, and source electrodes SE and drain electrodes DE are arrangedbetween the gate pads GP arranged on the right and left sides. Morespecifically, a source pad SP extending in an X-axial direction isinterposed between the gate pads GP arranged on the right and leftsides, and the plurality of comb-shaped source electrodes SE is formedto protrude from the source pad SP in a Y-axial direction.

Likewise, a drain pad DP extending in the X-axial direction is arrangedin a space between the gate pads GP disposed on the right and leftsides, and the plurality of comb-shaped drain electrodes DE is formed toprotrude from the drain pad DP in the Y-axial direction.

The plurality of source electrodes SE and the plurality of drainelectrodes DE are alternately arranged in the X-axial directionorthogonal to the Y-axial direction. In this case, a plurality of gateelectrodes GE extending in the Y-axial direction are arranged betweenthe respective source electrodes SE and the respective drain electrodesDE, which are alternately arranged. The gate electrodes GE areelectrically connected to a gate line GL that is juxtaposed in proximityto the source pad SP, and the gate line GL extending in the X-axialdirection is electrically connected to the gate pads GP arranged on theright and left sides of the paper plane.

Further, in the power MOSFET of the related art, a single ohmicelectrode OE1 is formed over a lower layer of the source electrodes SE,and the ohmic electrode OE1 is arranged to extend in the Y-axialdirection. The ohmic electrode OE1 is electrically connected to thesource electrodes SE formed over an upper layer thereof.

Likewise, a single ohmic electrode OE2 is formed over a lower layer ofthe drain electrodes DE, and the ohmic electrode OE2 is arranged toextend in the Y-axial direction. The ohmic electrode OE2 is electricallyconnected to the drain electrodes DE formed over an upper layer thereof.

FIG. 2 is a cross-sectional view taken along a line A-A in FIG. 1. Asillustrated in FIG. 2, in the power MOSFET of the related art, a bufferlayer BF is formed over a semiconductor substrate 1S made of, forexample, silicon, and a channel layer CH made of, for example, GaN isformed over the buffer layer BF. An electron supply layer ES made of,for example, AlGaN is formed over the channel layer CH.

In this example, the buffer layer BF is formed for the purpose ofreducing mismatching between lattice spacing of Silicon (Si) configuringthe semiconductor substrate 1S and lattice spacing of gallium nitride(GaN) configuring the channel layer CH. That is, when the channel layerCH made of gallium nitride (GaN) is formed directly on the semiconductorsubstrate 1S made of silicon, a large number of crystal defects areformed in the channel layer CH, to thereby lead to a performancedegradation of the power MOSFET. For that reason, the buffer layer BF isinserted for the purpose of reducing lattices between the semiconductorsubstrate 1S and the channel layer CH. With the formation of the bufferlayer BF, the quality of the channel layer CH formed over the bufferlayer BF can be improved. As a result, the performance of the powerMOSFET can be improved.

Subsequently, as illustrated in FIG. 2, the gate line GL and the ohmicelectrode OE1 are formed over the electron supply layer ES, and aninterlayer insulating film IL formed of, for example, a silicon oxidefilm is formed to cover the gate line GL and the ohmic electrode OE1. Acontact hole CNT is formed in the interlayer insulating film IL toexpose a surface of the ohmic electrode OE1, and the source electrode SEis embedded in the contact hole CNT and formed over the interlayerinsulating film IL. Further, the source pad SP is formed integrally withthe source electrodes SE over the interlayer insulating film IL, and thedrain pad DP is formed over the interlayer insulating film IL which isdistant from the source pad SP.

In the power MOSFET thus configured in the related art, a developmentusing a compound semiconductor process goes ahead, but in order torealize a reduction in the costs, the establishment of a mass productiontechnology in a silicon semiconductor process is demanded.

For example in the compound semiconductor process, a laminated filmincluding Ti, Al, Mo, and Au from a lower layer in the stated order isused for the ohmic electrode OE1 that comes in ohmic contact with anitride semiconductor layer, and a gold (Au) wire is used for a wire(for example, source electrode SE) that is electrically connected to theohmic electrode OE1.

Accordingly when a power device made of a nitride semiconductor materialis manufactured in the compound semiconductor process, the manufacturingcosts rise because expensive gold (Au) is frequently used. On the otherhand, in the silicon semiconductor process, because the expensive goldis not usually used for the interconnect layers, the manufacturing costscan be reduced.

When the silicon semiconductor process is used, because there is a needto suppress the diffusion of gold atoms, the ohmic electrode OE1 needsto be made of a material instead of the ohmic electrode OE1 including agold film. For example, it is conceivable that an aluminum filmexemplifies a metal material that comes in ohmic contact with thenitride semiconductor layer, and the ohmic electrode OE1 mainlycontaining the aluminum film therein is used in the siliconsemiconductor process. In particular, the present inventors have foundthat when the electron supply layer ES is made of AlGaN, and the ohmicelectrode is made of aluminum, since a work function of AlGaN and a workfunction of aluminum relatively approach each other, an excellent ohmiccontact can be formed.

However, according to the present inventors' study, when the ohmicelectrode OE1 is formed of the aluminum film, it is found that a room ofimprovement which will be described below is actualized, which will bedescribed.

Room for Improvement Present in the Related Art

A path of a current flowing when the power MOSFET is on in the relatedart will be described with reference to FIGS. 1 and 2. First, asillustrated in FIG. 1, when the power MOSFET is on, an on-state currentflows into the drain electrodes DE from the drain pad DP. Then, theon-state current that has reached the drain electrodes DE arrives at aninterface between the channel layer CH and the electron supply layer ESthrough the ohmic electrode OE2 formed over the lower layer of the drainelectrodes DE.

In this example, in the power MOSFET of the related art using thenitride semiconductor material, two dimensional electron gas isgenerated in the vicinity of the interface between the channel layer CHand the electron supply layer ES in the channel layer CH. The twodimensional electron gas is generated by the following mechanism. Sincean electron affinity of gallium nitride (GaN) configuring the channellayer CH and an electron affinity of aluminum gallium nitride (AlGaN)configuring the electron supply layer ES are different from each other,a conduction band offset (conduction band discontinuity) is formed. Asquare well potential lower than a Fermi level is generated in thevicinity of the interface between the channel layer CH and the electronsupply layer ES in the channel layer CH due to an influence theconduction band offset, and a piezoelectric polarization and aspontaneous polarization which are present in the channel layer CH andthe electron supply layer ES. As a result, electrons are accumulated inthe square well potential. With this configuration, the two dimensionalelectron gas is generated in the vicinity of the interface between thechannel layer CH and the electron supply layer ES.

Accordingly, as illustrated in FIG. 1, with the two dimensional electrongas generated in the interface between the channel layer CH and theelectron supply layer ES, the on-state current flows along the interfacebetween the channel layer CH and the electron supply layer ES, from alower layer of the ohmic electrode OE2 toward a lower layer of the ohmicelectrode OE1 through immediately below the gate electrodes. Thereafter,as illustrated in FIG. 2, the on-state current that has reached thelower layer of the ohmic electrode OE1 flows into the ohmic electrodeOE1 formed over the upper layer of the electron supply layer ES, and thesource electrodes SE formed over the ohmic electrode OE1, and finallyarrives at the source pad SP. In this way, in the power MOSFET of therelated art, the on-state current flows from the drain pad DP into thesource pad SP.

In this situation, as illustrated in FIG. 2, since the ohmic electrodeOE1 is configured by a single electrode, and extends in the Y-axialdirection, a part of the on-state current flows into the ohmic electrodeOE1 in the Y-axial direction. That is, a part of the on-state currentflows along a longitudinal direction of the ohmic electrode OE1.Likewise, as illustrated in FIG. 1, a part of the on-state current flowsinto not only the ohmic electrode OE1, but also the ohmic electrode OE2along a longitudinal direction of the ohmic electrode OE2.

For example, when attention is paid to the ohmic electrode OE1illustrated in FIG. 2, a part of the on-state current continues to flowfrom the right side toward the left side (in a longitudinal direction)illustrate in FIG. 2. Because a large current is used in the powerMOSFET, a current density flowing in the longitudinal direction of theohmic electrode OE1 becomes large in the power MOSFET of the relatedart. Under the above conditions, when the aluminum film is used for theohmic electrode OE1, electromigration is actualized. That is, becausethe aluminum film has a characteristic that the electromigration isliable to be generated when a current density of the current flowinginto the film increases, when the aluminum film is used as the ohmicelectrode OE1, there is a risk that the electromigration is generated inthe aluminum film, thereby inducing disconnection of the ohmic electrodeOE1.

The disconnection of the ohmic electrode OE1 is thus induced, the powerMOSFET comes to a defect. That is, when the density of current flowinginto the aluminum film becomes higher, there occurs the electromigrationwhich is a phenomenon that aluminum atoms obtain a momentum due to anelectron flow, and migrates toward a downstream side. When theelectromigration is generated, voids are generated within the aluminumfilm to cause the disconnection, or a hillock is generated downstream ofthe electron flow to degrade the reliability. Accordingly, in theabove-mentioned related art, when the ohmic electrode OE1 and the ohmicelectrode OE2 are each formed of the aluminum film, it is found thatthere is a room for improvement from the viewpoint of the reliability ofthe power MOSFET.

Under the circumstances, the first embodiment is configured with animprovement in the above-mentioned related art. Hereinafter, adescription will be given of a technical concept of the first embodimentthus configured.

Configuration of Semiconductor Device According to First Embodiment

FIG. 3 is a plan view illustrating a configuration example of a powerMOSFET (semiconductor device) according to the first embodiment. Asillustrated in FIG. 3, in the power MOSFET according to the firstembodiment, gate pads GP are each arranged on the right end and the leftend of the paper plane, and the source electrodes SE and the drainelectrodes DE are arranged between the gate pads GP arranged on theright and left sides. More specifically, the source pad SP extending inthe X-axial direction is arranged to be interposed between the gate padsGP arranged on the right and left sides, and the plurality of thecomb-shaped source electrodes (source comb-shaped electrodes) SE areformed to protrude from the source pad SP in the Y-axial direction.

Likewise, the drain pad DP extending in the X-axial direction isarranged in a space between the gate pads GP disposed on the right andleft sides, and the plurality of comb-shaped drain electrodes (draincomb-shaped electrodes) DE is formed to protrude from the drain pad DPin the Y-axial direction.

The plurality of source electrodes SE and the plurality of drainelectrodes DE are alternately arranged in the X-axial directionorthogonal to the Y-axial direction. In this case, a plurality of gateelectrodes GE extending in the Y-axial direction are arranged betweenthe respective source electrodes SE and the respective drain electrodesDE, which are alternately arranged. The plurality of gate electrodes GEare electrically connected to a gate line GL that is juxtaposed inproximity to the source pad SP, and the gate line GL extending in theX-axial direction is electrically connected to the gate pads GP arrangedon the right and left sides of the paper plane.

Further, in the power MOSFET of the first embodiment, an ohmic electrodeOE1 is formed over a lower layer of the source electrodes SE. The ohmicelectrode OE1 is configured by a plurality of unit electrodes UE1, andthe plurality of unit electrodes UE1 are aligned in the Y-axialdirection to form the ohmic electrode OE1. Each of the unit electrodesUE1 configuring the ohmic electrode OE1 is electrically connected to thesource electrodes SE formed over an upper layer thereof.

Likewise, an ohmic electrode OE2 is formed over a lower layer of thedrain electrodes DE. The ohmic electrode OE2 is configured by aplurality of unit electrodes UE2. The unit electrodes UE1 are aligned inthe Y-axial direction to form the ohmic electrode OE2. Each of the unitelectrodes UE2 configuring the ohmic electrode OE2 is electricallyconnected to the drain electrodes DE formed over an upper layer thereof.

In the first embodiment, a width of the source electrodes SE in theX-axial direction is equal to a width of the drain electrodes DE in theX-axial direction. The number of unit electrodes UE1 formed over thelower layer of the source electrodes SE is equal to the number of unitelectrodes UE2 formed over the lower layer of the drain electrodes DE.Because a source current and a drain current are substantially identicalin current value with each other, it is desirable that the number ofunit electrodes UE1 is the same as the number of unit electrodes UE2from the viewpoint of suppressing the electromigration. However,particularly in an intended purpose of decreasing a source resistance,the number of unit electrodes UE1 can be reduced more than the number ofunit electrodes UE2. Thus, the number of unit electrodes UE1 can differfrom the number of unit electrodes UE2 depending on the intendedpurpose.

FIG. 4 is a partially enlarged plan view of the source electrode SEillustrated in FIG. 3. As illustrated in FIG. 4, an interlayerinsulating film (not shown) is formed over the lower layer of the sourceelectrodes SE formed into a rectangular shape, and the plurality of unitelectrodes UE1 are formed through opening portions OP1 formed in theinterlayer insulating film. In this case, each of the unit electrodesUE1 and each of the opening portions OP1 are formed into a rectangularshape, and the plurality of unit electrodes UE1 are formed to beincluded by the source electrode SE in a plan view. Further, the openingportions OP1 are formed to be included by the unit electrodes UE1 in theplan view. That is, a size of the unit electrodes UE1 is smaller than asize of the source electrodes SE, and larger than a size of the openingportion OP1. This configuration is applied to not only a relationship ofthe source electrodes SE, the opening portions OP1, and the unitelectrodes UE1, but also a relationship of the drain electrodes DE, theopening portions (not shown), and the unit electrodes UE2 illustrated inFIG. 3.

Thus, in the first embodiment, in a direction (X-axial direction) alongwhich the plurality of unit electrodes UE1 are aligned, each width ofthe unit electrodes UE1 is larger than each width of the openingportions (first opening portions) OP1. Likewise, in a direction (X-axialdirection) along which the plurality of unit electrodes UE2 are aligned,each width of the unit electrodes UE2 is larger than each width of theopening portions (second opening portions). In the plan view, each ofthe opening portions OP1 is included in each of the unit electrodes UE1,and in the plan view, each of the plurality of opening portions isincluded in each of the plurality of unit electrodes UE2.

FIG. 5 is a cross-sectional view taken along a line A-A in FIG. 3. Asillustrated in FIG. 5, in the power MOSFET of the first embodiment, forexample, the buffer layer BF is formed over the semiconductor substrate1S made of, for example, silicon, and the channel layer CH made of, forexample, GaN is formed over the buffer layer BF. The electron supplylayer ES made of, for example, AlGaN is formed over the channel layerCH.

In this example, the buffer layer BF is formed for the purpose ofreducing mismatching between lattice spacing of Silicon (Si) configuringthe semiconductor substrate 1S and lattice spacing of gallium nitride(GaN) configuring the channel layer CH. That is, when the channel layerCH made of gallium nitride (GaN) is formed directly on the semiconductorsubstrate 1S made of silicon, a large number of crystal defects areformed in the channel layer CH, to thereby lead to a performancedegradation of the power MOSFET. For that reason, the buffer layer BF isinserted for the purpose of reducing lattices between the semiconductorsubstrate 1S and the channel layer CH. With the formation of the bufferlayer BF, the quality of the channel layer CH formed over the bufferlayer BF can be improved. As a result, the performance of the powerMOSFET can be improved.

In the first embodiment, an example in which the semiconductor substrate1S is made of silicon (Si) is described. However, the present inventionis not limited to this example, but the substrate may be made of siliconcarbide (SiC), sapphire (Al₂O₃), Gallium nitride (GaN), or diamond (C).

Subsequently, as illustrated in FIG. 5, in the power MOSFET of the firstembodiment, there is formed a trench (groove) TR that exceeds aninterface between the electron supply layer ES and the channel layer CHfrom a surface of the electron supply layer ES, and reaches the channellayer CH. A gate insulating film GOX formed of, for example, a siliconoxide film or an aluminum oxide film is formed on an inner wall of thetrench TR, and the gate electrodes GE is embedded within the trench TRthrough the gate insulating film GOX.

Also, as illustrated in FIG. 5, each unit electrode UE1 and each unitelectrode UE2 are formed over the electron supply layer ES, and aprotective film PRO formed of, for example, a silicon oxide film, and aninterlayer insulating film IL are formed to cover the unit electrode UE1and the unit electrode UE2. In the protective film PRO and theinterlayer insulating film IL, the opening portion OP1 is formed toexpose a surface of the unit electrode UE1, and an opening portion OP2is formed to expose a surface of the unit electrode UE2. Each sourceelectrode SE is formed over the interlayer insulating film IL from aninterior of the opening portion OP1. Likewise, each drain electrode DEis formed over the interlayer insulating film IL from an interior of theopening portion OP2. In this situation, the unit electrode UE1 and theunit electrode UE2 are each formed of an aluminum film, and the sourceelectrode SE and the drain electrode DE are each formed of a laminatedfilm including, for example, a barrier conductor film formed of atitanium/titanium nitride film, and an aluminum alloy film representedby an AlCu film or an AlSiCu film.

In the power MOSFET of the first embodiment using the nitridesemiconductor material thus configured, the two dimensional electron gasis generated in the vicinity of the interface between the channel layerCH and the electron supply layer ES. That is, the square well potentiallower than the Fermi level is generated in the vicinity of the interfacebetween the channel layer CH and the electron supply layer ES due to aninfluence of the conduction band offset based on a difference in theelectron affinity between the channel layer CH and the electron supplylayer ES, and the piezoelectric polarization and the spontaneouspolarization existing in the channel layer CH and the electron supplylayer ES. As a result, electrons are accumulated within the square wellpotential whereby the two dimensional electron gas is generated in thevicinity of the interface between the channel layer CH and the electronsupply layer ES.

The reason why the trench TR in which the gate electrode GE is embeddedexceeds the interface between the channel layer CH and the electronsupply layer ES, and reaches the channel layer CH is as follows. Forexample, when the gate electrode GE is arranged over the electron supplylayer ES, the two dimensional electron gas is generated in the interfacebetween the channel layer CH and the electron supply layer ESimmediately below the gate electrode GE even in a state where no voltageis applied to the gate electrode GE. That is, even in the state where novoltage is applied to the gate electrode GE, when a potential differenceoccurs between the drain electrode DE and the source electrode SE, anormally on-state in which the on-state current flows is obtained.

That is, when the channel layer CH and the electron supply layer ES aremade of nitride semiconductor, a bottom of the square well potential ispushed down due to the piezoelectric polarization and the spontaneouspolarization caused by using the nitride semiconductor in addition tothe square well potential caused by the conduction band offset betweenthe channel layer CH and the electron supply layer ES. As a result, whenthe gate electrodes GE have no trench structure, even if no voltage isapplied to the gate electrodes GE, the two dimensional electron gas isgenerated in the vicinity of the interface between the channel layer CHand the electron supply layer ES. As a result, the device becomes anormally-on type.

Incidentally, in a power control transistor represented by the powerMOSFET, the normally-on device is required. For that reason, asillustrated in FIG. 5, the power MOSFET having a structure in which thegate electrode GE is embedded in the trench TR is proposed.

In the power MOSFET having the gate electrode GE of the above trenchstructure, the interface between the channel layer CH and the electronsupply layer ES is interrupted by the gate electrode GE of the trenchstructure. For that reason, if the voltage to be applied to the gateelectrodes GE is equal to or lower than a threshold voltage, there is noconduction between the source electrodes SE and the drain electrodes DEdue to the two dimensional electron gas.

On the other hand, in the power MOSFET of the first embodiment, when avoltage equal to or higher than the threshold voltage is applied to thegate electrodes GE, electrons are collected in the vicinity of a bottomsurface of the gate electrodes GE to form an accumulation region due toa positive voltage applied to the gate electrodes GE. As a result, whenthe voltage equal to or higher than the threshold voltage is applied tothe gate electrodes GE, a conduction between the source electrodes SEand the drain electrodes DE is performed by the two dimensional electrongas and the accumulation region. As a result, an on-state current flowsfrom the drain electrodes DE toward the source electrodes SE. In otherwords, electrons flow from the source electrodes SE toward the drainelectrodes DE. In this way, in the power MOSFET configured asillustrated in FIG. 5, the normally-off device can be realized. That is,the gate electrodes GE of the trench structure are applied for thepurpose of realizing the normally-off device.

As illustrated in FIG. 5, the unit electrode UE1 and the unit electrodeUE2 are formed over the electron supply layer ES. The electron supplylayer (nitride semiconductor layer) ES and the unit electrode UE1, orthe electron supply layer (nitride semiconductor layer) ES and the unitelectrode UE2 come in ohmic contact with each other.

FIG. 6 is a graph illustrating a current to voltage characteristic inthe ohmic contact. Referring to FIG. 6, the axis of abscissa representsa voltage to be applied between the ohmic contacts, and the axis ofordinate represents a current that flows between the ohmic contacts. Asillustrated in FIG. 6, when a first voltage is applied to the ohmiccontact, a current in a positive direction linearly rises with anincrease in the first voltage. On the other hand, when a second voltageis applied to the ohmic contact, a current in a negative directionlinearly rises with an increase in the second voltage. From this face,it is understood that in the current to voltage characteristic of theohmic contact, the current to voltage characteristic in a first voltagepolarity is completely identical with the current to voltagecharacteristic in a second voltage polarity. That is, the ohmic contactis a resistive contact which is defined as a contact having norectification characteristic as with a Schottky contact.

Features of First Embodiment

FIG. 7 is a cross-sectional view of the source electrode SE mainly takenalong a B-B line of FIG. 3. In the first embodiment, the structure inwhich the source electrode SE is taken along a section line extending inthe Y-axial direction, and the structure in which the drain electrodesDE is taken along a section line extending in the Y-axial direction havethe same configuration. Therefore, in the following description,attention is paid to the source electrodes SE. The following structureis applicable to not only the source electrodes SE and a structureimmediately below the source electrodes SE, but also the drainelectrodes DE and a structure immediately below the drain electrodes DE.

As illustrated in FIG. 7, in the power MOSFET of the first embodiment,the buffer layer BF is formed over the semiconductor substrate 1S madeof, for example, silicon, and the channel layer CH made of, for example,GaN is formed over the buffer layer BF. The electron supply layer ESmade of, for example, AlGaN is formed over the channel layer CH.

The plurality of unit electrodes UE1 are aligned over the electronsupply layer ES in the Y-axial direction. The ohmic electrode OE1 isformed by those unit electrodes UE1. Further, the protective film PROformed of, for example, a silicon oxide film, and the interlayerinsulating film IL are formed to cover the ohmic electrode OE1. Also,the gate line GL is formed over the protective film PRO, and the gateline GL is covered with the interlayer insulating film IL.

The plurality of opening portions OP1 are formed in the protective filmPRO and the interlayer insulating film IL to expose the respectivesurfaces of the plurality of unit electrodes UE1 configuring the ohmicelectrode OE1. The source electrodes SE are formed over the interlayerinsulating film IL from the interior of the opening portions OP1, andthe source pad SP is formed integrally with the source electrodes SE.Also, the drain pad DP is also formed over the interlayer insulatingfilm IL to be separated from the source electrodes SE so as to beelectrically isolated from the source electrodes SE. In this case, theunit electrodes UE1 are each formed of an aluminum film, and the sourceelectrodes SE are each formed of a laminated film including, forexample, a barrier conductor film formed of a titanium/titanium nitridefilm, and an AlCu film or an AlSiCu film.

The feature of the first embodiment resides in that the ohmic electrodeOE1 is configured by the plurality of divided unit electrodes UE1. Withthis configuration, the electromigration resistance in the ohmicelectrode OE1 can be improved.

For example, in the related art, as illustrated in FIG. 2, the ohmicelectrode OE1 is configured by a single body. That is, in the relatedart, since the ohmic electrode OE1 extends in the Y-axial direction, apart of the on-state current flows into the ohmic electrode OE1 alongthe Y-axial direction (negative direction). In this case, electrons areaccelerated by an electric field within the ohmic electrode OE1, andafter the electrons are accelerated to some extent, the electronscollide with metal ions configuring the ohmic electrode OE1. A kineticenergy of the electrons are converted into a lattice vibration energy(thermal energy) of the metal ions, and also converted into the kineticenergy of the metal ions.

On the other hand, the metal ions are thermalized at a substantiallyfixed position of a periodic potential, and can migrate beyond a wall ofthe potential with a certain probability. The wall of the potential isgenerally called “activation energy”, and a value is substantiallydetermined according to a material.

Because the metal ions that exceed the wall of the potential naturallyreturn to an original position, or migrate at random, the metal is notchanged macroscopically. However, when the kinetic energy of electronsaccelerated by an electric field is supplied to the metal ions, themetal ions configuring the ohmic electrode OE1 migrate along a flow ofthe electrons in the same direction (direction along which the electronsflow) at the same time. As a result, as the number of electronsaccelerated by the electric field is increased, voids are generated inthe ohmic electrode OE1, and a disconnection occurs in a worse case.

That is, in the related art, as illustrated in FIG. 2, because the ohmicelectrode OE1 is configured by a single body extending in the Y-axialdirection, a current density of the on-state current that flows into theohmic electrode OE1 along the Y-axial direction (negative direction) isincreased. As a result, the metal ions configuring the ohmic electrodeOE1 migrate in one direction along which the electrons flow at the sametime, by a flow of the electrons configuring the on-state current. As aresult, in the related art, the ohmic electrode OE1 is liable to bedisconnected.

On the contrary, as illustrated in FIG. 7, the ohmic electrode OE1according to the first embodiment is not configured by a single body,but configured by a plurality of unit electrodes UE1 divided to beseparated from each other. That is, the ohmic electrode OE1 according tothe first embodiment is configured by the plurality of divided unitelectrodes UE1 which are separated in the Y-axial direction. As aresult, according to the ohmic electrode OE1 of the first embodiment, apart of the on-state current can be prevented from flowing into theohmic electrode OE1 along the Y-axial direction (negative direction).

That is, in the first embodiment, because the ohmic electrode OE1 isconfigured by the plurality of divided unit electrodes UE1 which areseparated from each other, the on-state current can be prevented fromflowing across the plurality of unit electrodes UE1 in the Y-axialdirection (negative direction). Further, in each of the plurality ofunit electrodes UE1, the current density of the on-state current flowingin the Y-axial direction (negative direction) can be prevented fromincreasing.

As a result, according to the first embodiment, since the ohmicelectrode OE1 is configured by the plurality of divided unit electrodesUE1 which are separated from each other, the electromigration resistanceof the ohmic electrode OE1 can be improved. That is, in the firstembodiment, because the ohmic electrode OE1 is divided into theplurality of unit electrodes UE1, the current density of the currentflowing in the ohmic electrode OE1 in the Y-axial direction(longitudinal direction) can be suppressed as compared in the relatedart.

Referring to FIG. 7, arrows indicate paths in which the on-state currentflows immediately below the source electrodes SE. As indicated by thearrows, the on-state current flows into the ohmic electrode OE1 arrangedover the electron supply layer ES after having flowing in the interfacebetween the channel layer CH and the electron supply layer ES. In thiscase, as illustrated in FIG. 7, because the ohmic electrode OE1 isconfigured by the plurality of divided unit electrodes UE1 which areseparated from each other along the Y-axial direction, the on-statecurrent is diverged into the plurality of unit electrodes UE1, andflows. Since the plurality of ohmic electrodes OE1 are separated fromeach other in the Y-axial direction, the on-state current can beprevented from flowing into the ohmic electrode OE1 along the Y-axialdirection (negative direction). In other words, because the ohmicelectrode OE1 is configured by the plurality of divided unit electrodesUE1 which are separated from each other, the on-state current can beeffectively prevented from flowing across the plurality of unitelectrodes UE1 in the Y-axial direction (negative direction). Further,in each of the plurality of unit electrodes UE1, the current density ofthe on-state current flowing in the Y-axial direction (negativedirection) can be prevented from increasing. As a result, theelectromigration can be prevented from being generated in the ohmicelectrode OE1.

Thereafter, the on-state current flowing in each of those unitelectrodes UE1 flows into the source electrodes SE from the openingportions OP1 formed in the respective unit electrodes UE1, and flowsfrom the source electrodes SE into the source pad SP.

In this example, as illustrated in FIG. 7, the source electrodes SE areelectrically connected to the respective unit electrodes UE1, and extendin the Y-axial direction. From this fact, in the source electrodes SE,the on-state currents that have flown in the plurality of unitelectrodes UE1 join together, and flow. Accordingly, there is a concernabout the degradation of the electromigration resistance in the sourceelectrodes SE. However, in the first embodiment, there is no need toconcern about this drawback.

This is because in the first embodiment, the source electrodes SE is notconfigured by an aluminum (Al) film, but configured by an aluminum alloyfilm represented by an AlCu film or an AlSiCu film. For example, in thecase of the AlCu film, a slight amount of copper (Cu) of several % orlower which is heavier than aluminum (Al) is added to the AlCu film. Inthis case, copper (Cu) has a function of being deposited on a crystalgrain boundary of aluminum (Al), and adhering the respective crystalgrains of aluminum (Al) to each other. As a result, in the AlCu film,the electromigration resistance can be improved. That is, because thesource electrodes SE are each formed of an AlCu film higher in theelectromigration resistance than the aluminum film, or the AlSiCu film,the occurrence of voids or the disconnection caused by theelectromigration can be sufficiently suppressed in the source electrodesSE.

Further, for example, a thickness of the AlCu film and a thickness ofthe AlSiCu film, which configure the source electrodes SE, are about 4.5μm whereas a thickness of the aluminum film configuring the ohmicelectrode OE1 (unit electrode UE1) is about 0.3 μm. Accordingly, becausethe thickness of the AlCu film configuring the source electrodes SE issufficiently thicker than the thickness of the ohmic electrode OE1 (unitelectrodes UE1), the voids and the disconnection caused by theelectromigration are difficult to generate.

Thus, in the source electrodes SE, because the AlCu film or the AlSiCufilm which is higher in the electromigration resistance than thealuminum film is used, and the thickness of the AlCu film and thethickness of the AlSiCu film are thick, the occurrence of voids and thedisconnection caused by the electromigration are not actualized.

Accordingly, a configuration in which the ohmic electrode OE1 is alsoformed of the aluminum alloy film represented by, for example, the AlCufilm or the AlSiCu film is useful with the application of theabove-mentioned technique. That is, since the plurality of unitelectrodes UE1 are each formed of the aluminum alloy film in addition tothe feature that the ohmic electrode OE1 is configured by the pluralityof divided unit electrodes UE1 which are separated from each other(feature of the first embodiment), the electromigration resistance canbe further improved. As a result, according to the first embodiment, thepower MOSFET very high in the reliability can be provided.

Method of Manufacturing Semiconductor Device According to FirstEmbodiment

The semiconductor device (power MOSFET) according to the firstembodiment is configured as described above, and a method ofmanufacturing the semiconductor device will be described with referenceto the drawings. In the method of manufacturing the semiconductor devicedescribed below will be first described with reference to across-sectional view taken along a line A-A in FIG. 3, and thereafterdescribed with reference to a cross-sectional view taken along a lineB-B of FIG. 3 showing the feature of the first embodiment.

As illustrated in FIG. 8, for example, a semiconductor layer structureis formed over the semiconductor substrate 1S made of silicon having a(111) surface exposed, through a metal organic chemical vapor deposition(MOCVD). In the semiconductor layer structure, the buffer layer BF madeof, for example, undoped gallium nitride (GaN) is formed. Subsequently,the channel layer CH made of undoped gallium nitride (GaN) is formedover the buffer layer BF. Thereafter, the electron supply layer ES madeof undoped (AlGaN) is formed over the channel layer CH. In this manner,the semiconductor layer structure is formed. The semiconductor layerstructure is formed by the growth of a group-III surface laminated in acrystal axis (C-axis) direction.

Subsequently, as illustrated in FIG. 9, a metal film MF1 formed of, forexample, an aluminum film is formed over the electron supply layer ES.The metal film MF1 can be formed through, for example, a sputteringtechnique. Thereafter, as illustrated in FIG. 10, the metal film MF1 ispatterned through a photolithography and an etching technique. As aresult, the unit electrodes UE1 (ohmic electrode OE1) and the unitelectrodes UE2 (ohmic electrode OE2) which are each formed of the metalfilm MF1 can be formed over the electron supply layer ES. The unitelectrodes UE1 and the unit electrodes UE2 are formed to be separatedfrom each other.

Subsequently, as illustrated in FIG. 11, the protective film PRO isformed over the electron supply layer ES on which the unit electrodesUE1 and the unit electrodes UE2 are formed. The protective film PRO isformed to cover the unit electrodes UE1 and the unit electrodes UE2, andformed of, for example, a silicon oxide film.

Thereafter, as illustrated in FIG. 12, the trench (groove) TR thatpenetrates through the protective film PRO and the electron supply layerES and reaches the channel layer CH is formed through thephotolithography and the etching technique. The trench TR is formedbetween the unit electrodes UE1 and the unit electrodes UE2.

Subsequently, as illustrated in FIG. 13, the gate insulating film GOX isformed over a part of the protective film PRO from an inner wall of thetrench TR, and the gate electrodes GE formed of, for example, apolysilicon film or a metal film is formed over the gate insulating filmGOX so as to fill the interior of the trench TR. In this situation, thegate insulating film GOX can be formed of, for example, the siliconoxide film, but is not limited to this configuration, and may be formedof a high dielectric constant film higher in dielectric constant thanthe silicon oxide film.

For example, the high dielectric constant film is formed of an aluminumoxide film (Al₂O₃ film), or a hafnium oxide film (HfO₂ film) which isone of hafnium oxides. However, the hafnium oxide film may be replacedwith the other hafnium insulating films such as a hafnium aluminatefilm, an HfON film (hafnium oxynitride film), an HfSiO film (hafniumsilicate film), an HfSiON film (hafnium silicon oxynitride film), and anHfALO film. Further, the high dielectric constant film can be formed ofa hafnium insulating film in which oxide such as tantalum oxide, niobiumoxide, titanium oxide, zirconium oxide, lanthanum oxide, or yttriumoxide is introduced into those hafnium insulating films. Since thehafnium insulating film is high in the dielectric constant than thesilicon oxide film or a silicon oxynitride film as with the hafniumoxide film, a leak current can be reduced as with a case using thehafnium oxide film.

Subsequently, as illustrated in FIG. 14, the interlayer insulating filmIL is formed over the gate electrodes GE and the protective film PRO.The interlayer insulating film IL can be formed of, for example, thesilicon oxide film. Thereafter, as illustrated in FIG. 15, the openingportions OP1 and the opening portions OP2 that penetrate through theinterlayer insulating film IL and the protective film PRO are formedthrough the photolithography and the etching technique. The openingportions OP1 are formed to expose the surface of the unit electrodesUE1, and the opening portions OP2 are formed to expose the surface ofthe unit electrodes UE2.

Subsequently, as illustrated in FIG. 16, a barrier conductor film(barrier metal film) BMF formed of, for example, a titanium/titaniumnitride film is formed over the interlayer insulating film IL having theopening portions OP1 and the opening portions OP2 formed therein, and ametal film MF2 formed of, for example, an aluminum alloy filmrepresented by an AlCu film or an AlSiCu film is formed over the barrierconductor film BMF. The barrier conductor film BMF and the metal filmMF2 can be formed through the sputtering technique.

Thereafter, as illustrated in FIG. 17, the metal film MF2 and thebarrier conductor film BMF are patterned through the photolithographyand the etching technique. As a result, the source electrodes SE can beembedded in the interior of the opening portions OP1, and formed over apart of the interlayer insulating film IL. Likewise, the drainelectrodes DE can be embedded in the interior of the opening portionsOP2, and formed over a part of the interlayer insulating film IL. As aresult, the source electrodes SE can be formed to be electricallyconnected to the unit electrodes UE1, and the drain electrodes DE can beformed to be electrically connected to the unit electrodes UE2. With theabove process, the semiconductor device (power MOSFET) according to thefirst embodiment can be formed.

Subsequently, the method of manufacturing the semiconductor device willbe described from the viewpoints of clarifying the feature in the firstembodiment. More specifically, the method of manufacturing thesemiconductor device according to the first embodiment will be describedbelow with reference to a cross-sectional view taken along a line B-B inFIG. 3.

First, through the process described with reference to FIG. 8, thesemiconductor layer structure illustrated in FIG. 18 is formed. Then, asillustrated in FIG. 19, the metal film MF1 formed of, for example, thealuminum film is formed over the electron supply layer ES formed over anuppermost layer of the semiconductor layer structure.

Thereafter, as illustrated in FIG. 20, the metal film MF1 is patternedthrough the photolithography and the etching technique to form aplurality of unit electrodes UE1. Those unit electrodes UE1 areseparated from each other, and the ohmic electrode OE1 is formed bythose plural unit electrodes UE1. In this way, in the first embodiment,the ohmic electrode OE1 can be configured by the plurality of unitelectrodes UE1.

Subsequently, as illustrated in FIG. 21, the protective film PRO isformed over the electron supply layer ES on which the plurality of unitelectrodes UE1 are formed. The protective film PRO can be formed of, forexample, the silicon oxide film, and formed through a CVD (chemicalvapor deposition) technique.

Subsequently, after the gate line GL has been formed over the protectivefilm PRO as illustrated in FIG. 22, the interlayer insulating film IL isformed over the protective film PRO on which the gate line GL is formedas illustrated in FIG. 23. The interlayer insulating film IL can beformed of, for example, the silicon oxide film, and formed through, forexample, the CVD technique.

Thereafter, as illustrated in FIG. 24, the plurality of opening portionsOP1 that penetrate through the interlayer insulating film IL and theprotective film PRO are formed through the photolithography and theetching technique. The plurality of opening portions OP1 are formed soas to expose the respective surfaces of the plurality of unit electrodesUE1.

Then, as illustrated in FIG. 25, the barrier conductor film BMF formedof, for example, the titanium/titanium nitride film is formed over theinterlayer insulating film IL in which the opening portions OP1 areformed, and the metal film MF2 formed of, or example, the aluminum alloyfilm represented by the AlCu film or the AlSiCu film is formed over thebarrier conductor film BMF. The barrier conductor film BMF and the metalfilm MF2 can be formed through, for example, the sputtering technique.

Thereafter, the metal film MF2 and the barrier conductor film BMF arepatterned through the photolithography and the etching technique. As aresult, the source electrodes SE can be embedded in the interior of theopening portions OP1, and formed over a part of the interlayerinsulating film IL. Further, the source pad SP integrated with thesource electrodes SE, and the drain pad DP separated to be electricallyisolated from the source electrodes SE are formed in the same process.With the above process, the semiconductor device (power MOSFET) in thefirst embodiment can be manufactured.

Typical Advantages of First Embodiment

The semiconductor device according to the first embodiment can obtaintypical advantages described below.

(1) According to the first embodiment, in a process of manufacturing thepower MOSFET made of the nitride semiconductor material, the siliconsemiconductor process can be applied. This means that the use of themetal film used in the compound semiconductor process can be reduced, asa result of which the manufacturing costs of the power MOSFET in thefirst embodiment can be reduced.

(2) In this case, the ohmic electrode OE1 (OE2) formed between the powerMOSFET made of the nitride semiconductor material, and the interconnectlayers (source electrodes SE and drain electrodes DE) is formed of thealuminum film instead of a film including the metal film.

As a result, in the power MOSFET dealing with a large current, there isa concern about the occurrence of voids and the disconnection caused bythe electromigration in the ohmic electrode OE1 (OE2).

Regarding this matter, in the first embodiment, the ohmic electrode OE1is configured by the plurality of divided unit electrodes UE1 which areseparated from each other, and the ohmic electrode OE2 is configured bythe plurality of divided unit electrodes UE2 which are separated fromeach other. For that reason, the on-state current can be effectivelyprevented from flowing across the plurality of unit electrodes UE1 orthe plurality of unit electrodes UE2 in the Y-axial direction (negativedirection). Further, in each of the plurality of unit electrodes UE1 andeach of the plurality of unit electrodes UE2, the current density of theon-state current flowing in the Y-axial direction (negative direction)can be prevented from increasing.

As a result, the electromigration can be prevented from being generatedin the ohmic electrode OE1 and the ohmic electrode OE2.

Therefore, according to the power MOSFET of the first embodiment, theoccurrence of voids and the disconnection caused by the electromigrationcan be effectively suppressed, as a result of which the reliability ofthe semiconductor device can be improved.

(3) For example, it is assumed that a drain current density (on-statecurrent density) in the power MOSFET according to the first embodimentis 0.2 A/mm (the drain current density per 1 mm is 0.2 A in a gate widthdirection of the gate electrode (direction perpendicular to a channel).Further, it is assumed that a length of the unit electrodes UE1 (UE2)configuring the ohmic electrode OE1 (OE2) in the longitudinal directionis 2 mm, a length thereof in a direction orthogonal to the longitudinaldirection 4 μm, and a gap interval between the divided unit electrodesUE1 (UE2) is μm. The calculation results under those conditions areillustrated in FIG. 26. FIG. 26 illustrates a relationship between thecurrent density (A/cm2) (the current density indicates a value in a unitcross-section perpendicular to the direction along which the currentflows), and the number of divisions (the number of unit electrodes) ofunit electrodes UE1 (UE2).

As illustrated in FIG. 26, it is found that the current density becomessmaller as the number of divisions of the unit electrodes UE1 (UE2) isincreased more. For example, in the ohmic electrode OE1 (OE2), when itis assumed that an allowable current density in which the occurrence ofvoids and the disconnection caused by the electromigration are generatedis 1×10⁵ (A/cm²), the current density becomes 2.5×10⁶ (A/cm²) which ishigher than the allowable current density by a single digit or more inthe number of divisions 0 (corresponding to the related art). On thecontrary, for example, if the number of unit electrodes is set to 24 ormore, the current density can be reduced more than the allowable currentdensity. As a result, the ohmic electrode OE1 (OE2) is configured by theplurality of divided unit electrodes UE1 (UE2) which are separated fromeach other, with the result the ohmic electrode OE1 (OE2) higher in theelectromigration resistance can be realized.

(4) Further, in the first embodiment, the source electrodes SEelectrically connected to the ohmic electrode OE1, or the drainelectrodes DE electrically connected to the ohmic electrode OE2 areformed of the aluminum alloy film represented by the AlCu film or theAlSiCu film which is higher in the electromigration resistance than thealuminum film. From this fact, in the first embodiment, theelectromigration resistance can be improved in the source electrodes SEand the drain electrodes DE. In particular, in the first embodiment, thesource electrodes SE and the drain electrodes DE are each formed of alaminated film of a high melting point metal film and an aluminum alloyfilm represented by a titanium film. Therefore, even if breakage causedby the electromigration is generated in the aluminum alloy film, becausean electric connection caused by the high melting point metal film isensured, the disconnection of the source electrodes SE and the drainelectrodes DE can be suppressed.

(5) As described above, the first embodiment has a first feature thatthe ohmic electrode OE1 is configured by the plurality of divided unitelectrodes UE1 which are separated from each other, and the ohmicelectrode OE2 is configured by the plurality of divided unit electrodesUE2 which are separated from each other. Also, the first embodiment hasa second feature that the source electrodes SE and the drain electrodesDE are each formed of the aluminum alloy film represented by the AlCufilm or the AlSiCu film. From this fact, in the first embodiment, in thepower MOSFET having the ohmic electrode OE1 (OE2) and the sourceelectrodes SE (drain electrodes DE), separately, the electromigrationresistance can be improved with the provision of the above-mentionedfirst feature and second feature. As a result, according to the firstembodiment, the reliability of the power MOSFET having the ohmicelectrode OE1 (OE2) and the source electrodes SE (drain electrodes DE),separately, can be improved.

First Modification

In the first embodiment, an example in which the unit electrodes UE1(UE2) divided from each other are each formed of a single layer filmmade of the aluminum film is described. In a first modification, anexample in which the unit electrodes UE1 (UE2) divided from each otherare each formed of a laminated film having the titanium film and thealuminum film will be described.

FIG. 27 is a diagram illustrating a cross-section of a power MOSFETaccording to the first modification. The configuration of FIG. 27 issubstantially identical with that of FIG. 7 illustrating the firstembodiment, and therefore a different feature will be described.

The feature of the first modification resides in that as illustrated inFIG. 27, each of the plurality of unit electrodes UE1 configuring theohmic electrode OE1 is formed of a laminated film including a titaniumfilm TI1, an aluminum film AL, and a titanium film TI2. With thisconfiguration, according to the first modification, the reliability ofthe semiconductor device can be further improved as compared with thefirst embodiment.

For example, in the first modification, as with the first embodiment,since the ohmic electrode OE1 is configured by the plurality of dividedunit electrodes UE1 which are separated from each other, theelectromigration resistance can be improved. If the number of unitelectrodes UE1 is small, as illustrated in FIG. 26, it is assumed thatthe current density of the on-state current (drain current) becomeshigher than the allowable current density. In this case, there is apossibility that the breakage caused by the electromigration isgenerated in the unit electrodes UE1.

However, in the first modification, even if the breakage caused by theelectromigration is generated in the aluminum film AL configuring theunit electrodes UE1, the electric connection is ensured by the titaniumfilm ill and the titanium film 112 formed to sandwich the aluminum filmAL therebetween. As a result, the disconnection of the unit electrodesUE1 can be prevented. Therefore, according to the first modification,the reliability of the semiconductor device (power MOSFET) can befurther improved by synergistic effects of the feature that the ohmicelectrode OE1 is configured by the plurality of divided unit electrodesUE1 with the feature that each of the plurality of unit electrodes UE1is formed of the laminated film including the titanium film TI1, thealuminum film AL, and the titanium film TI2.

In particular, there is a case in which voids are generated in thealuminum film AL by the electromigration even if the aluminum film AL isbroken. In this case, although the unit electrodes UE1 are notdisconnected, the above-mentioned voids may be generated immediatelybelow the opening portions OP1. In this case, if the titanium film 112is not formed over the upper surface of the aluminum film AL, there is arisk that the electric connection between the source electrodes SE andthe unit electrodes UE1 is cut by the voids formed immediately below theopening portions OP1. Regarding this matter, in the first modification,because the titanium film 112 is formed over the upper layer of thealuminum film AL, even if the voids are generated in the aluminum filmAL immediately below the opening portions OP1, the electric connectionbetween the source electrodes SE and the unit electrodes UE1 is ensuredby the titanium film 112 formed over the upper layer of the aluminumfilm AL. As a result, according to the first modification, thereliability of the semiconductor device (power MOSFET) can be furtherimproved.

Second Modification

In the first embodiment, for example, as illustrated in FIG. 3, a casein which the width of the source electrodes SE in the X-axial directionis equal to the width of the drain electrodes DE in the X-axialdirection is described. In a second modification, an example in whichthe width of the source electrodes SE in the X-axial direction is equalto the width of the drain electrodes DE in the X-axial direction will bedescribed.

FIG. 28 is a diagram illustrating a plan configuration of the powerMOSFET according to the second modification. The configuration of FIG.28 is substantially identical with that of FIG. 3 illustrating the firstembodiment, and therefore a different feature will be described.

A feature of the second modification resides in that the number of unitelectrodes UE1 disposed over the lower layer of the source electrodes SEis different from the number of unit electrodes UE2 disposed over thelower layer of the drain electrodes DE. More specifically, in the secondmodification, the number (four in FIG. 28) of unit electrodes UE1disposed over the lower layer of the source electrodes SE is larger thanthe number (three in FIG. 28) of unit electrodes UE2 disposed over thelower layer of the drain electrodes DE. This is because of the followingreasons.

For example, in the second modification, as illustrated in FIG. 28, awidth L1 of the source electrodes SE in the X-axial direction is smallerthan a width L2 of the drain electrodes DE in the X-axial direction. Inthis case, in the power MOSFET according to the second modification, thecurrent density of the on-state current that flows in the drainelectrodes DE is lower than the current density of the on-state currentthat flows in the source electrodes SE. In other words, the currentdensity of the on-state current that flows in the source electrodes SEis larger than the current density of the on-state current that flows inthe drain electrodes DE. This means that in a layout configuration ofthe second modification illustrated in FIG. 28, the ohmic electrode OE1formed over the lower layer of the source electrodes SE is lower in theelectromigration resistance than the ohmic electrode OE2 formed over thelower layer of the drain electrodes DE. From this fact, in the secondmodification, the number of the plurality of unit electrodes UE1configuring the ohmic electrode OE1 lower in the electromigrationresistance is made larger than the number of the plurality of unitelectrodes UE2 configuring the ohmic electrode OE2, to thereby lessenthe current density in each of those unit electrodes UE1.

That is, as illustrated in FIG. 28, when the width L1 of the sourceelectrodes SE in the X-axial direction is smaller than the width L2 ofthe drain electrodes DE in the X-axial direction, the current density inthe ohmic electrode OE1 disposed over the lower layer of the sourceelectrodes SE become largest. For that reason, the number of theplurality of unit electrodes UE1 configuring the ohmic electrode OE1 isincreased with the results that the current density in the unitelectrodes UE1 is reduced to improve the electromigration resistance.

In the second modification, the case in which the width L1 of the sourceelectrodes SE in the X-axial direction is smaller than the width L2 ofthe drain electrodes DE in the X-axial direction is described.Conversely, it is conceivable that the width L1 of the source electrodesSE in the X-axial direction is larger than the width L2 of the drainelectrodes DE in the X-axial direction. In this case, the currentdensity in the ohmic electrode OE2 disposed over the lower layer of thedrain electrodes DE becomes largest. For that reason, the number of theplurality of unit electrodes UE2 configuring the ohmic electrode OE2 isincreased more than the number of the plurality of unit electrodes UE1configuring the ohmic electrode OE1, as a result of which the currentdensity in the unit electrodes UE2 can be reduced to improve theelectromigration resistance.

Third Modification

In the first embodiment, for example, as illustrated in FIG. 3, theexample in which the layout arrangement of the plurality of unitelectrodes UE1 formed over the lower layer of the source electrodes SEis identical with the layout arrangement of the plurality of unitelectrodes UE2 formed over the lower layer of the drain electrodes DE isdescribed. In a third modification, an example in which the layoutarrangement of the plurality of unit electrodes UE1 formed over thelower layer of the source electrodes SE is shifted from the layoutarrangement of the plurality of unit electrodes UE2 formed over thelower layer of the drain electrodes DE will be described.

FIG. 29 is a diagram illustrating a plan configuration of the powerMOSFET according to the third modification. The configuration of FIG. 29is substantially identical with that of FIG. 3 illustrating the firstembodiment, and therefore a different feature will be described.

A feature of the third modification resides in that, as illustrated inFIG. 29, a planar layout configuration of the plurality of unitelectrodes UE1 formed over the lower layer of the source electrodes SEis different from a planar layout configuration of the plurality of unitelectrodes UE2 formed over the lower layer of the drain electrodes DE.

Also, in this case, the same advantages as those in the first embodimentcan be obtained. That is, in the third modification, as in the firstembodiment, the ohmic electrode OE1 is configured by the plurality ofdivided unit electrodes UE1 which are separated from each other, and theohmic electrode OE2 is configured by the plurality of divided unitelectrodes UE2 which are separated from each other. For that reason, inthe third modification, as in the first embodiment, the on-state currentcan be effectively prevented from flowing across the plurality of unitelectrodes UE1 or the plurality of unit electrodes UE2 in the Y-axialdirection (negative direction). Further, in each of the plurality ofunit electrodes UE1 and each of the plurality of unit electrodes UE2,the current density of the on-state current flowing in the Y-axialdirection (negative direction) can be prevented from increasing. As aresult, the electromigration can be prevented from being generated inthe ohmic electrode OE1 and the ohmic electrode OE2. Therefore,according to the power MOSFET of the third modification, the occurrenceof voids and the disconnection caused by the electromigration can beeffectively suppressed, as a result of which the reliability of thesemiconductor device can be improved.

Second Embodiment

In the first embodiment, the example in which the material filled in theopening portions OP1 is the same as the material of the sourceelectrodes SE formed over the interlayer insulating film IL isdescribed. In a second embodiment, an example in which the materialfilled in the opening portions is different from the material of thesource electrodes formed over the interlayer insulating film will bedescribed. Likewise, in the second embodiment, an example in which thematerial filled in the opening portions is different from the materialof the drain electrodes formed over the interlayer insulating film willbe described.

Configuration of Semiconductor Device According to Second Embodiment

FIG. 30 is a diagram illustrating a cross-section of a power MOSFETaccording to the second embodiment. The configuration of FIG. 30 issubstantially identical with that of FIG. 7 illustrating the firstembodiment, and therefore a different feature will be mainly described.

As illustrated in FIG. 30, the protective film PRO is formed to coverthe plurality of unit electrodes UE1, and an insulating film IF1 isformed over the protective film PRO. Then, an insulating film IF2 isformed over the insulating film IF1. An interlayer insulting film IL1 isconfigured by the insulating film IF1 and the insulating film IF2. Theinsulating film IF1 is formed of, for example, a silicon oxide film, andthe insulating film IF2 is formed of, for example, a silicon nitridefilm.

The plurality of opening portions OP1 are formed in the interlayerinsulting film IL1 thus configured and the protective film PRO so as topenetrate through the interlayer insulting film IL1 and the protectivefilm PRO, and reach the respective surfaces of the plurality of unitelectrodes UE1. Plugs PLG1 are each formed within the opening portionsOP1. The plug PLG1 includes a barrier conductor film BMF2 formed of atitanium/titanium nitride film which is formed on an inner wall of theopening portions OP1, and a tungsten film WF formed over the barrierconductor film BMF2 and embedded in the opening portions OP1.

Then, the source electrodes SE are formed over the interlayer insultingfilm IL1 in which the plugs PLG1 are formed, and the source pad SP isformed integrally with the source electrodes SE over the interlayerinsulting film IL1. In this situation, the source electrodes SE areelectrically connected to the plurality of unit electrodes UE1 by theplugs PLG1 formed to be embedded in the interlayer insulting film IL1.Also, the drain pad DP separated from the source electrodes SE andelectrically isolated from the source electrodes SE is also formed overthe interlayer insulting film IL1. The source electrodes SE, the sourcepad SP, and the drain pad DP are each formed of, for example, a barrierconductor film BMF3, and a metal film MF3 represented by an AlCu filmformed over the barrier conductor film BMF3, or an AlSiCu film.

Thus, the power MOSFET according to the second embodiment is differentfrom the first embodiment in which the material filled in the openingportions OP1 is the same as the material of the source electrodes SE inthat, for example, the material of the source electrodes SE is differentfrom the material of the plugs PLG1. Likewise, in the second embodiment,although not shown, for example, the material of the drain electrodes isdifferent from the material of the plugs.

Also, in the power MOSFET according to the second embodiment, since theohmic electrode OE1 is configured by the plurality of divided unitelectrodes UE1 which are separated from each other, the same advantagesas those in the first embodiment can be obtained.

Method of Manufacturing Semiconductor Device According to SecondEmbodiment

The semiconductor device (power MOSFET) according to the secondembodiment is configured as described above, and a method ofmanufacturing the semiconductor device will be described below withreference to the drawings.

First, the processes illustrated in FIGS. 18 to 22 are identical withthose in the first embodiment. Subsequently, as illustrated in FIG. 31,the insulating film IF1 is formed over the protective film PRO, and theinsulating film IF2 is formed over the insulating film IF1. Theinsulating film IF1 can be formed of, for example, a silicon oxide film,and formed through, for example, the CVD technique. Also, the insulatingfilm IF2 can be formed of, for example, a silicon nitride film, andformed through, for example, the CVD technique.

Then, as illustrated in FIG. 32, the plurality of opening portions OP1are formed to penetrate through the insulating film IF2, the insulatingfilm IF1, and the protective film PRO, and reach the respective surfacesof the plurality of unit electrodes UE1 through the photolithography andthe etching technique.

Thereafter, as illustrated in FIG. 33, the barrier conductor film BMF2formed of, for example, a titanium/titanium nitride film is formed overthe insulating film IF2 included within the opening portions OP1, andthe tungsten film WF is formed over the barrier conductor film BMF2 andembedded in the opening portions OP1. The barrier conductor film BMF2 isformed through, for example, the sputtering technique, and the tungstenfilm WF is formed through, for example, the CVD technique.

Subsequently, as illustrated in FIG. 34, the unnecessary barrierconductor film BMF2 and the unnecessary tungsten film WF, which areformed over the insulating film IF2, are removed through, for example, achemical mechanical polishing (CMP). As a result, the barrier conductorfilm BMF2 and the tungsten film WF remain only in the opening portionsOP1 to form the plugs PLG1. Thereafter, as illustrated in FIG. 35, thebarrier conductor film BMF3 formed of, for example, a titanium/titaniumnitride film is formed over the insulating film IF2 in which the plugsPLG1 are formed, and the metal film MF3 formed of, for example, an AlCufilm or an AlSiCu film is formed over the barrier conductor film BMF3.In this situation, the barrier conductor film BMF3 and the metal filmMF3 can be formed through, for example, the sputtering technique.

Then, the metal film MF3 and the barrier conductor film BMF3 arepatterned through the photolithography and the etching technique. As aresult, the source electrodes SE, the source pad SP, and the drain padDP can be formed as illustrated in FIG. 30. With the above processes,the semiconductor device (power MOSFET) according to the secondembodiment can be manufactured.

Third Embodiment

In a third embodiment, an applied example of the power MOSFET describedin the first embodiment and the second embodiment will be described.

Inverter Circuit Example

The semiconductor device according to the third embodiment is used in adriver circuit of a three-phase motor used in, for example, a hybridvehicle. FIG. 36 is a diagram illustrating a circuit diagram of thethree-phase motor according to the third embodiment. Referring to FIG.36, a three-phase motor circuit includes a three-phase motor 1, a powersemiconductor device 2, and a control circuit 3. The three-phase motor 1is driven by a voltage of three phases different in phase. The powersemiconductor device 2 is configured by a switching element thatcontrols the three-phase motor 1. For example, power MOSFETs 4 anddiodes 5 are disposed in correspondence with, for example, three phases.That is, in each single phase, the power MOSFETs 4 and the diodes 5 areconnected in antiparallel between a supply potential (Vcc) and an inputpotential of the three-phase motor, and the power MOSFETs 4 and thediodes 5 are also connected in antiparallel between the input potentialof the three-phase motor and a ground potential (GND). That is, in thethree-phase motor 1, two of the power MOSFETs 4 and two of the diodes 5are disposed for each single phase (each phase), and six of the powerMOSFETs 4 and six of the diodes 5 are disposed for three phases. Gateelectrodes of the individual power MOSFETs 4 are connected with thecontrol circuit 3 although not partially shown, and the power MOSFETs 4are controlled by the control circuit 3. In the driver circuit of thethree-phase motor thus configured, a current that flows in the powerMOSFETs 4 (switching elements) configuring the power semiconductordevice 2 is controlled by the control circuit 3, to thereby rotate thethree-phase motor 1. That is, the power MOSFETs 4 function as theswitching elements for applying the supply potential (Vcc) to thethree-phase motor 1, or applying the ground potential (GND) thereto, andtiming of turning on/off the power MOSFETs 4 is controlled by thecontrol circuit 3, to thereby drive the three-phase motor 1.

The power MOSFETs 4 and the diodes 5 are connected in antiparallel asillustrated in FIG. 36, and a function of the diodes in this situationwill be described.

When a load is a pure resistor with no inductance, the diodes 5 areunnecessary because there is no return energy. However, when a circuithaving the inductance such as a motor (for example, three-phase motor)is connected to the load, there is a mode in which a load current flowsin an opposite direction to the switch (for example, power MOSFET 4)that is on. For that reason, there is a need to connect the diodes tothe switching elements such as the power MOSFETs 4 in antiparallel. Thatis, in the inverter circuit, when the load includes the inductance aswith the motor control, when the switching element such as the powerMOSFET 4 turns off, an electric energy (½LI²) stored in the inductancemust be discharged. Under the circumstances, in order to allow theelectric energy stored in the inductance to flow back, the diodes 5 areconnected in antiparallel to the power MOSFETs 4. That is, the diodes 5have a function of allowing a reverse current to flow for the purpose ofreleasing the electric energy stored in the inductance.

According to the semiconductor device thus-configured in the thirdembodiment, the use of the power MOSFET described in the firstembodiment and the second embodiment can reduce the costs and canimprove the reliability of the semiconductor device.

Fourth Embodiment

A power MOSFET according to a fourth embodiment is different from thepower MOSFET of the first and second embodiments in only the gateelectrode structure in the X-axial direction. In FIG. 5 which is across-section taken along a line A-A of FIG. 3, the trench TR is formed,and the gate insulating film GOX that covers the inner wall of thetrench TR, and the gate electrodes GE that come in contact with the gateinsulating film GOX are formed.

On the other hand, in the fourth embodiment, as illustrated in FIG. 37,a p-type GaN cap layer PC is formed in contact with the electron supplylayer ES, and a gate electrode GE2 is formed over the p-type GaN caplayer PC. It is desirable that the p-type GaN cap layer PC and the gateelectrode GE2 are connected by Schottky connection. A gate insulatingfilm (not shown) formed of an insulating film may be formed between thep-type GaN cap layer PC and the gate electrode GE2. In this example, itis desirable that the p-type GaN cap layer PC is formed inside the gateelectrode GE2 in a plan view.

In the fourth embodiment, because the p-type GaN cap layer PC which is ap-type semiconductor layer is inserted between the gate electrode GE2and the electron supply layer ES, a threshold voltage can be set to bepositive. That is, in the fourth embodiment, because the normally-offoperation can be realized without formation of the trench TR, themanufacturing costs can be reduced.

The invention made by the present inventors has been describedspecifically on the basis of the embodiments. However, the presentinvention is not limited to the above embodiments, but can be variouslychanged without departing from the spirit of the invention.

What is claimed is:
 1. A semiconductor device including a field effecttransistor, the field effect transistor comprising: (a) a galliumnitride semiconductor layer; (b) a gate electrode formed over thegallium nitride semiconductor layer and extending in a first directionin a plan view; (c) a first ohmic electrode arranged at one side of thegate electrode and including a plurality of first patterns, theplurality of first patterns being in ohmic contact with the galliumnitride semiconductor layer, being separated from each other, and beingarranged in the first direction in a plan view; (d) a second ohmicelectrode arranged at the other side of the gate electrode and includinga plurality of second patterns, the plurality of second patterns beingin ohmic contact with the gallium nitride semiconductor layer, beingseparated from each other, and being arranged in the first direction ina plan view; (e) an insulating film formed to cover the first ohmicelectrode and the second ohmic electrode, the insulating film having aplurality of first openings to expose surfaces of the plurality of firstpatterns and having a plurality of second openings to expose surfaces ofthe plurality of second patterns; (f) a source electrode pattern formedon the insulating film, the source electrode pattern being electricallyand commonly connected to the plurality of first patterns of the firstohmic electrode; and (g) a drain electrode pattern formed on theinsulating film, the drain electrode pattern being electrically andcommonly connected to the plurality of second patterns of the secondohmic electrode.
 2. The semiconductor device according to claim 1,wherein the first ohmic electrodes and the second ohmic electrodes eachinclude an aluminum film.
 3. The semiconductor device according to claim1, wherein each of the source electrode pattern and the drain electrodepattern is extended in the first direction.
 4. The semiconductor deviceaccording to claim 1, wherein the source electrode pattern and the firstpatterns form a source electrode of the field effect transistor, andwherein the drain electrode pattern and the second patterns form a drainelectrode of the field effect transistor.
 5. The semiconductor deviceaccording to claim 1, wherein the source electrode pattern and the drainelectrode pattern each include an aluminum film.
 6. The semiconductordevice according to claim 1, wherein the first ohmic electrodes and thesecond ohmic electrodes each include a laminate film having an aluminumfilm sandwiched between titanium films.
 7. The semiconductor deviceaccording to claim 1, wherein the source electrode pattern and the drainelectrode pattern each include an aluminum alloy film.
 8. Thesemiconductor device according to claim 7, wherein the aluminum alloyfilm includes one of an AlCu film and an AlSiCu film.
 9. Thesemiconductor device according to claim 1, wherein the ohmic contact isa resistive contact having no rectification.